High performance RISC CPU
49 instructions
Instruction cycle selectable: 1T / 2T / 4T
62.5ns @1T, 16MHz, VDD ≥ 2.7V
storage architecture
Program ROM : 8k x 14 bits
Data RAM : 1k x 8 bits
Data EEPROM: 256 x 8 bits
Sector program code protection ( sector =1k x 14bits)
Support IAP , VDD ≥ 2.7V
16 layer hardware stack
Special Microcontroller Features
Operating temperature range: -40 ─ 85°C
Wide operating voltage range: 1.9 ─ 5.5V
DC – 8MHz: VDD ≥ 1.9V
DC – 16MHz: VDD ≥ 2.7V
clock source
16MHz High speed and high precision HIRC
32kHz Low Speed Low Power LIRC
Crystal oscillator and external clock input
Crystal Clock Missing Detection
Two-Speed Clock Startup in Crystal Clock Configuration
Slow Clock Period Measurement
band 7 16- bit prescaler Bit watchdog, clock source selectable
Power-on reset delay counter
Low power consumption mode SLEEP
System clock can be optionally kept running or turned off
Low Voltage Reset LVR:
2.0, 2.2, 2.5, 2.8, 3.1, 3.6, 4.1V
Low voltage detection LVD:
Internal voltage: 2.0 , 2.4 , 2.8 , 3.0 , 3.6 , 4.0V
Or detect external input, can be used as a comparator
support ISP and online debugging OCD
3 hardware breakpoint
Soft reset, single step, pause, jump, etc.
Package : SOP16, TSSOP20, SOP20, SOP24, TSSOP24, SOP28, LQFP32, QFN32
Peripheral Features
GPIOs
30 General-purpose IO with independent control of each direction
30 pins with independent pull-up control
30 pins with independent pull-up control
30 wake-up pins: edge or level detection
30 Programmable source current pins: 2/4/14/26mA@5V
30 Programmable current sink pins: max. 62mA@5V
Supports remapping of pins with secondary functions
Communication Interface
USART
I2C, Master and slave
SPI, Master and slave
12 bit SAR ADC (x1)
8 external channels + 1 ¼ _ VDD aisle
Internal reference voltage: VDD, 0.5V , 2V , 3V
External references: VREFP , VREFN
Manual and automatic triggering methods
Support delay trigger
Supports automatic calibration
TIM1-16bit
belt 16 16- bit prescaler bit timer
auto reload
Clock source: system clock, HIRC and a multiplied clock ( crystal or HIR C double frequency ) , LIRC
Period, duty cycle register double buffer design
4 independent capture / compare /PWM aisle
PWM Supports edge-aligned, center-aligned, and one- shot modes
3 Complementary PWM with Deadband Control output
leading edge blanking
Fail Brake Control
TIM2-16bit
belt 15 16- bit prescaler bit timer
auto reload
Clock source: system clock, HIRC and a multiplied clock ( crystal or HIR C double frequency ) , LIRC
Period, duty cycle register double buffer design
3 independent capture / compare /PWM aisle
TIM4-8bit , with 8bit prescaler base timer, Clock source optional
Touch Sensing Module
15 key channel
The number of scans can be configured
water-proof
Selection table
Chip Version History
Table of contents in this site
- System Function Block Diagram and Pin 17
1.1. Footprint 18
1.2. Pin Description 21 - program memory 22
2.1. Read program memory as data memory 22
2.1.1. RETW command 23
2.1.2. use FSR indirect read 23 - data memory 24
3.1. Data memory configuration 24
3.1.1. Kernel Register 25
3.1.2. Status Register 25
3.2. Special Function Register 26
3.2.1. universal RAM 26
3.2.2. GPR The linear access of 26
3.2.3. public RAM 27
3.2.4. Memory area address mapping 28
3.2.5. Bank11 , bank12 and bank31 30
3.2.6. Bank31 The shadow register 31
3.3. Stack 31
3.3.1. access stack 32
3.3.2. Overflow / Underflow Reset 32
3.4. Indirect Addressing 33
3.4.1. Legacy Data Storage33
3.4.2. Linear Data Memory 34
3.4.3. Flash program memory 35 - reset source 36
4.1. Power On Reset 36
4.1.1. Power-on reset process 37
4.2. Low Voltage Reset 38
4.3. Power-on reset delay 38
4.4. Illegal instruction reset 39
4.5. Software Reset 39
4.6. EMC Reset 39
4.7. Power-on configuration process (BOOT) 39
4.7.1. can be triggered BOOT Summary of Process Reset Sources 40
4.8. LVD Low Voltage Detection 40
4.8.1. Detect external voltage 40
4.8.2. LVD Interrupt 40
4.9. Reset Timing 41
4.9.1. Power-on reset sequence 1 41
4.9.2. Power-on reset sequence 2 41
4.9.3. Power-on reset sequence 3 42
4.10. Reset source flag bit 42
4.10.1. PCON register, address 0x96 43
4.10.2. LVDCON register, address 0x199 44
4.11. Configuration Register Summary 45
4.11.1. UCFG0 , PROM address 0x8000 45
4.11.2. UCFG1 , PROM address 0x8001 46
4.11.3. UCFG2 , PROM address 0x8002 47
4.11.4. UCFG3 , PROM address 0x8003 48
4.11.5. DCFG0 , PROM address 0x8047 48 - clock source 49
5.1. Clock Source Mode 49
5.2. External Clock Mode 50
5.2.1. Oscillator Start-up Timer ( OST ) 50
5.2.2. EC mode 50
5.2.3. LP and XT mode 50
5.2.4. Internal Clock Mode 50
5.2.5. Frequency Select Bits ( MCKCF ) 51
5.2.6. HIRC and LIRC Clock Switching Timing 51
5.2.7. HIRC Clock Special Functions 52
5.3. Clock Switching 52
5.3.1. System Clock Select ( SCS ) bit 52
5.3.2. Oscillator Start-up Time-Out Status ( OSTS ) Bit 53
5.3.3. Two-Speed Clock Startup Mode 53
5.3.4. Two-speed start mode configuration 53
5.3.5. Two-speed start sequence 54
5.3.6. Fail-Safe Clock Monitor 54
5.3.7. Failsafe Detection 54
5.3.8. Failsafe Operation 55
5.3.9. Failsafe Condition Clear 55
5.3.10. Reset or wake from sleep 55
5.4. Peripheral Clock Gating 56
5.5. Clock Out 56
5.5.1. Clock Output Note 57
5.6. Summary of Registers Related to Clock Sources 57
5.6.1. OSCCON register, address 0x99 58
5.6.2. OSCTUNE register, address 0x98 58
5.6.3. PCKEN register, address 0x9A 59
5.6.4. CKOCON register, address 0x95 60
5.6.5. TCKSRC register, address 0x31F 61 - Interrupt 62
6.1. Interrupt Enable 62
6.2. Interrupt response time 63
6.3. Interrupts under Sleep 63
6.4. Field Protection 63
6.5. Summary of Registers Related to Interrupts 64
6.5.1. INTCON register, address 0x0B 64
6.5.2. PIR1 register, address 0x11 65
6.5.3. PIE1 register, address 0x91 65 - sleep mode 66
7.1. Wake of Sleep 66
7.1.1. Wake up using an interrupt 67
7.2. sleep system clock 67
7.3. Summary of Registers Related to Sleep Mode 67 - data EEPROM and PROM68 _
8.1. EEADRL and EEADRH Register 68
8.1.1. EECON1 and EECON2 Register 69
8.2. use data EEPROM69 _
8.2.1. read data EEPROM Memory 69
8.2.2. write data EEPROM memory 70
8.2.3. Protective Measures Against Inadvertent Write Operation 70
8.2.4. about GIE Qing 0 70
8.3. Flash Program Memory Overview 72
8.3.1. READ FLASH PROGRAM MEMORY 72
8.3.2. ERASING FLASH PROGRAM MEMORY 73
8.3.3. Write Flash program memory 74
8.4. Modification of Flash Program Memory 75
8.5. configuration word UCFGx/FCFGx read access 76
8.6. Write verification 76
8.7. PROMs Content Protection76
8.8. and EEPROM Summary of Related Registers 77
8.8.1. EEDAT register, address 0x193, 0x194 77
8.8.2. EEADR register, address 0x191, 0x192 78
8.8.3. EECON1 register, address 0x195 79
8.8.4. EECON2 register, address 0x196 80
8.8.5. EECON3 register, address 0x198 80 - 12bit ADC Module 81
9.1 ADC configuration of 82
9.1.1 calibration ADC 82
9.1.2 port configuration 82
9.1.3 Channel selection 82
9.1.4 Trigger mode selection 83
9.1.5 Trigger source selection 83
9.1.6 Trigger type selection 83
9.1.7 Trigger delay configuration 83
9.1.8 ADC Reference voltage 83
9.1.9 Conversion Clock 84
9.1.10 Interrupt 85
9.1.11 Format of the conversion result 86
9.1.12 Threshold Comparison 86
9.2 ADC How it Works 87
9.2.1 Start Auto Calibration 87
9.2.2 boot conversion 87
9.2.3 Conversion done 87
9.2.4 Termination conversion 88
9.2.5 sleep mode ADC work 88
9.2.6 External Trigger 88
9.2.7 A/D Conversion Step 89
9.3 A/D Acquisition time requirement 90
9.4 and ADC Related Register Summary 91
9.4.1 ADRESL , address 0x9B 92
9.4.2 ADRESH , address 0x9C 92
9.4.3 ADCON0 , address 0x9D 93
9.4.4 ADCON1 , address 0x9E 94
9.4.5 ADCON2 , address 0x9F 95
9.4.6 ADDLY/LEBPRL , address 0x1F 95
9.4.7 ADCON3 , address 0x41A 96
9.4.8 ADCMPH , address 0x41B 96 - Advanced Timer TIM1 97
10.1. Features 97
10.2. Block Diagram 97
10.3. Functional description 98
10.3.1. Counting base unit 98
10.3.2. Counting controller 107
10.3.3. Capture compare channel 112
10.3.4. TIM1 Interrupt 125
10.3.5. Fault brake source 125
10.3.6. Leading Edge Blanking 127
10.4. and TIM1 Related Register Summary 128
10.4.1. TIM1CR1 , address: 0x211 129
10.4.2. TIM1SMCR , address: 0x213 130
10.4.3. TIM1IER , address: 0x215 131
10.4.4. TIM1SR1 , address: 0x216 132
10.4.5. TIM1SR2 , address: 0x217 133
10.4.6. TIM1EGR , address: 0x218 133
10.4.7. TIM1CCMR1 , address: 0x219 134
10.4.8. TIM1CCMR2 , address: 0x21A 136
10.4.9. TIM1CCMR3 , address: 0x21B 137
10.4.10. TIM1CCMR4 , address: 0x21C 138
10.4.11. TIM1CCER1 , address: 0x21D 139
10.4.12. TIM1CCER2 , address: 0x21E 140
10.4.13. TIM1CNTRH , address: 0x28C 140
10.4.14. TIM1CNTRL , address: 0x28D 140
10.4.15. TIM1PSCRH , address: 0x28E 140
10.4.16. TIM1PSCRL , address: 0x28F 141
10.4.17. TIM1ARRH , address: 0x290 141
10.4.18. TIM1ARRL , address: 0x291 141
10.4.19. TIM1RCR , address: 0x292 142
10.4.20. TIM1CCR1H , address: 0x293 142
10.4.21. TIM1CCR1L , address: 0x294 142
10.4.22. TIM1CCR2H , address: 0x295 143
10.4.23. TIM1CCR2L , address: 0x296 143
10.4.24. TIM1CCR3H , address: 0x297 143
10.4.25. TIM1CCR3L , address: 0x298 144
10.4.26. TIM1CCR4H , address: 0x299 144
10.4.27. TIM1CCR4L , address: 0x29A 144
10.4.28. TIM1BKR , address: 0x29B 145
10.4.29. TIM1DTR , address: 0x29C 146
10.4.30. TIM1OISR , address: 0x29D 146
10.4.31. LEBCON register, address 0x41C 147 - General purpose timer TIM2 148
11.1. Features 148
11.2. Block Diagram 148
11.3. Functional description 149
11.3.1. Counting Basic Units 149
11.3.2. Capture compare channel 150
11.3.3. TIM2 Interrupt 152
11.4. and TIM2 Related Register Summary 153
11.4.1. TIM2CR1 , address 0x30C 154
11.4.2. TIM2IER , address 0x30D 154
11.4.3. TIM2SR1 , address 0x30E 155
11.4.4. TIM2SR2 , address 0x30F 155
11.4.5. TIM2EGR , address 0x310 156
11.4.6. TIM2CCMR1 , address 0x311 157
11.4.7. TIM2CCMR2 , address 0x312 159
11.4.8. TIM2CCMR3 , address 0x313 160
11.4.9. TIM2CCER1 , address 0x314 161
11.4.10. TIM2CCER2 , address 0x315 161
11.4.11. TIM2CNTRH , address 0x316 162
11.4.12. TIM2CNTRL , address 0x317 162
11.4.13. TIM2PSCR , address 0x318 162
11.4.14. TIM2ARRH , address 0x319 162
11.4.15. TIM2ARRL , address 0x31A 163
11.4.16. TIM2CCR1H , address 0x31B 163
11.4.17. TIM2CCR1L , address 0x31C 163
11.4.18. TIM2CCR2H , address 0x31D 164
11.4.19. TIM2CCR2L , address 0x31E 164
11.4.20. TIM2CCR3H , address 0x29E 164
11.4.21. TIM2CCR3L , address 0x29F 164 - basic timer TIM4 165
12.1. Features 165
12.2. Block Diagram 165
12.3. TIM4 Clock source 165
12.4. Prescaler 165
12.5. TIM4 Interrupt 166
12.6. TIM4 Register Table 166
12.6.1. TIM4CR1 , address 0x111 167
12.6.2. TIM4IER , address 0x112 167
12.6.3. TIM4SR , address 0x113 168
12.6.4. TIM4EGR , address 0x114 168
12.6.5. TIM4CNTR , address 0x115 168
12.6.6. TIM4PSCR , address 0x116 169
12.6.7. TIM4ARR , address 0x117 169 - SPI Interface 170
13.1. Features 170
13.2. Functional description 170
13.2.1. General description 170
13.2.2. configuration SPI 173
13.2.3. Data processing flow 173
13.2.4. Sleep Mode Wakeup 174
13.2.5. CRC Processing flow 175
13.3. and SPI Related Register Summary 175
13.3.1. SPIDATA register, address 0x015 176
13.3.2. SPICTRL register, address 0x016 176
13.3.3. SPICFG register, address 0x017 177
13.3.4. SPISCR register, address 0x018 178
13.3.5. SPICCRCPOL register, address 0x019 178
13.3.6. SPIRXCRC register, address 0x01A 178
13.3.7. SPITXCRC register, address 0x01B 179
13.3.8. SPIIER register, address 0x01C 179
13.3.9. SPICTRL2 register, address 0x01D 180
13.3.10. SPISTAT register, address 0x01E 181 - I2C Interface 182
14.1. I2C How It Works 182
14.1.1. Host sends 183
14.1.2. The host receives 184
14.1.3. Slave sends 185
14.1.4. Slave receives 186
14.1.5. General Call 186
14.2. and I2C Summary of Related Registers 187
14.2.1. I2CCR1 register, address 0x40C 187
14.2.2. I2CCR2 register, address 0x40D 188
14.2.3. I2CCR3 register, address 0x40E 189
14.2.4. I2COARL register, address 0x40F 189
14.2.5. I2COARH register, address 0x410 189
14.2.6. I2CFREQ register, address 0x411 190
14.2.7. I2CDR register, address 0x412 190
14.2.8. I2CCMD register, address 0x413 191
14.2.9. I2CCCRL register, address 0x414 191
14.2.10. I2CCCRH register, address 0x415 192
14.2.11. I2CITR register, address 0x416 193
14.2.12. I2CSR1 Register, Address 0x417 194
14.2.13. I2CSR2 Register, Address 0x418 195
14.2.14. I2CSR3 Register, Address 0x419 196 - USART Interface 197
15.1. Features 197
15.2. Functional description 198
15.2.1. General description 198
15.2.2. Asynchronous Work Mode 199
15.2.3. Synchronous working mode 200
15.2.4. Half duplex mode 200
15.2.5. Infrared working mode 201
15.2.6. Smart Card Mode 202
15.2.7. LIN Master mode 203
15.2.8. Multi-chip communication mode 204
15.2.9. Auto baud rate detection 205
15.3. and USART Related Register Summary 206
15.3.1. URDATAL register, address 0x48C 206
15.3.2. URDATAH register, address 0x48D 206
15.3.3. URIER register, address 0x48E 207
15.3.4. URLCR register, address 0x48F 208
15.3.5. URLCREXT register, address 0x490 208
15.3.6. URMCR register, address 0x491 209
15.3.7. URLSR register, address 0x492 210
15.3.8. URRAR register, address 0x493 211
15.3.9. URDLL register, address 0x494 211
15.3.10. URDLH register, address 0x495 211
15.3.11. URABCR register, address 0x496 212
15.3.12. URSYNCR register, address 0x497 212
15.3.13. URLINCR register, address 0x498 213
15.3.14. URSDCR0 register, address 0x499 213
15.3.15. URSDCR1 register, address 0x49A 214
15.3.16. URSDCR2 register, address 0x49B 214
15.3.17. URTC register, address 0x49C 214 - Capacitive button module 215
16.1. Touch button function 215
16.2. Touch button structure 215
16.3. Touch key operation 217
16.4. Touch key interrupt 217
16.5. Programming Considerations 217
16.6. Working mode 218
16.6.1. single scan 218
16.6.2. Multiple scans 218
16.6.3. 4 Segment Hopping 218
16.7. and TOUCH Summary of Related Registers 219
16.7.1. TKTMR register, address 0x038C 221
16.7.2. TKC0 register, address 0x038D 221
16.7.3. TKC1 register, address 0x038E 222
16.7.4. TKMnC0 register , address 0x0396+2n(n=0~3) 223
16.7.5. TKMnC1 register , address 0x0397+2n(n=0~3) 224
16.7.6. CFnOUT1L register, address 0x0F8E+8n(n=0~3) 224
16.7.7. CFnOUT1H register, address 0x0F8F+8n(n=0~3) 225
16.7.8. CFnOUT2L register, address 0x0F90+8n(n=0~3) 225
16.7.9. CFnOUT2H register, address 0x0F91+8n(n=0~3) 225
16.7.10. CFnOUT3L register, address 0x0F92+8n(n=0~3) 226
16.7.11. CFnOUT3H register, address 0x0F93+8n(n=0~3) 226
16.7.12. TKMn16DL register, address 0x0F94+8n(n=0~3) 226
16.7.13. TKMn16DH register, address 0x0F95+8n(n=0~3) 227 - GPIO 228
17.1. port and TRIS Register 229
17.2. Weak pull-ups 229
17.3. Weak pulldown 229
17.4. Open drain output 229
17.5. ANSELA Register 230
17.6. Source current selection 230
17.7. Sink current selection 230
17.8. Priority of pin out 230
17.9. PORTx Functions and Priorities 231
17.10. Pin Function Remapping 232
17.11. External Interrupt 232
17.12. About the read port PORTx 233
17.13. Summary of Port-Related Registers 235
17.13.1. PSRC0 , Address 0x11A 236
17.13.2. PSRC1 , address 0x11B 236
17.13.3. PSINK0 , address 0x19A 236
17.13.4. PSINK1 , address 0x19B 237
17.13.5. PSINK2 , address 0x19C 237
17.13.6. PSINK3 , address 0x19D 237
17.13.7. ITYPE0 , address 0x11E 237
17.13.8. ITYPE1 , address 0x11F 238
17.13.9. AFP0 , Address 0x19E 238
17.13.10. AFP1 , address 0x19F 239
17.13.11. AFP2 , address 0x11D 239
17.13.12. EPS0 , address 0x118 240
17.13.13. EPS1 , address 0x119 240
17.13.14. EPIF0 , address 0x14 241
17.13.15. EPIE0 , address 0x94 241
17.13.16. ODCON0 , address 0x21F 241
17.13.17. PORTx , address 0x0C, 0D, 0E, 0F 242
17.13.18. TRISx , address 0x8C, 8D, 8E, 8F 242
17.13.19. LATx , address 0x10C, 10D, 10E, 10F 242
17.13.20. WPUx , address 0x18C, 18D, 18E, 18F 242
17.13.21. WPDx , address 0x20C, 20D, 20E, 20F 243
17.13.22. ANSELA , address 0x197 243 - Watchdog Timer 244
18.1. Watchdog clock source 245
18.2. Summary of registers related to watchdog 245
18.2.1. WDTCON register, address 0x97 246
18.2.2. MISC0 register, address 0x11C 247 - Slow Clock Measurements 248
19.1. Principles of Measurement 248
19.2. Power-on automatic measurement 249
19.3. Operation step 250
19.4. Summary of Registers Related to Slow Clock Measurements 250
19.4.1. MSCKCON register, address 0x41D 251
19.4.2. SOSCPR register, address 0x41E , 41F 251 - Instruction Set Summary 252
20.1. Read – Modify – Write ( RMW ) Instructions 253
20.1. Detailed instruction description 254 - Electrical Characteristics of Chips 264
21.1. Limit parameters 264
21.2. Built-in high-frequency oscillator ( HIRC ) 264
21.3. Built-in low frequency oscillator ( LIRC ) 264
21.4. Low Voltage Reset Circuit ( LVR ) 265
21.5. Low Voltage Detection Circuit ( LVD ) 265
21.6. Power On Reset Circuit ( POR ) 265
21.7. I/O PAD circuit 266
21.8. Overall operating current ( I DD ) 266
21.9. AC Electrical parameters 267
21.10. 12bit ADC Features 268
21.11. Memory Properties 269
21.12. DC and AC characteristic curves 269
21.12.1. HIRC vs VDD ( TA=25°C ) 269
21.12.2. LIRC vs VDD ( TA=25°C ) 270
21.12.3. different V DD Down, I DD vs Freq ( 1T, T A =25°C ) 270
21.12.4. different V DD Down, I DD vs Freq ( 2T, T A =25°C ) 271
21.12.5. different V DD Down, I SB ( sleep current ) Variation curve with temperature 271
21.12.6. At different temperatures , IOH ( level -2mA ) vs V OH @V DD =5V 272
21.12.7. At different temperatures , IOH ( level -4mA ) vs V OH @V DD =5V 272
21.12.8. At different temperatures , IOH ( level -14mA ) vs V OH @V DD =5V 273
21.12.9. At different temperatures , IOH ( level -26mA ) vs V OH @V DD =5V 273
21.12.10. At different temperatures, I OL ( L0 ) vs V OL @V DD =5V 274
21.12.11. At different temperatures, I OL ( L1) vs V OL @V DD =5V 274 - Chip Packaging Information 275
appendix 1 , document change history 282
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